1. Field of Invention
This invention pertains to thin film transistors and methods of fabrication thereof.
2. Related Art and Other Considerations
Heretofore it has been recognized that semiconductor memory devices operate in a certain mode that make it advantageous to employ an O-N-O structure. FIG. 3 shows a semiconductor memory device 300 comprising a single crystalline silicon semiconductor 302 covered with the following layers (in ascending order): a thin layer 304 of SiO.sub.2 ; a layer 306 of Si.sub.3 N.sub.4, and a second layer 308 of SiO.sub.2. A metal 310 is formed on the uppermost SiO.sub.2 layer 308 for serving as a gate of the memory device. It is the juxtaposition of the three layers of SiO.sub.2, Si.sub.3 N.sub.4, SiO.sub.2 that evokes the terminology "O-N-O".
In operation, in an O-N-O-utilizing semiconductor memory device it is desired that electrons from the single crystalline substrate 302 tunnel through SiO.sub.2 layer 304 and get trapped in the nitride layer (i.e., layer 306 of Si.sub.3 N.sub.4) when a predetermined voltage is applied to the gate metal 310. Consistent with this operation, SiO.sub.2 layer 304 is formed to be no more than a tunnel thickness thick (e.g., on the order of about 15 Angstroms). In operation of the memory device, the trapped charge in the Si.sub.3 N.sub.4 layer 306 acts according to the charge on gate metal 310.
In the aforedescribed manner, a bit of a semiconductor memory can be turned "on" or "off", and in the course of operation is switched many times between an "on" and "off" status. The repeated switching causes repeated electron tunneling through SiO.sub.2 layer 304. A figure of merit in the evaluation of semiconductor memories is the number of times the memory can switch before it ceases to act reliably. Such a memory can cease to function reliably if electrons tunneling through SiO.sub.2 layer 304 cause damage to SiO.sub.2 layer 304. Such damage is particularly prone when SiO.sub.2 layer 304 is experiencing strain.
It has been recognized that controlling the thickness of Si.sub.3 N.sub.4 layer 306 can lessen susceptibility of the SiO.sub.2 layer 304 to damage. In this regard, while the O-N interface (i.e., the interface at SiO.sub.2 layer 304 and Si.sub.3 N.sub.4 layer 306) serves to trap electrons, the remaining thickness of Si.sub.3 N.sub.4 layer 306 influences the reliability of the memory by providing a mechanical effect that lessens susceptibility of SiO.sub.2 layer 304 to strain damage. Hence the advantage of employing O-N-O structure in a semiconductor memory.
Electron travel in a thin film transistor ("TFT") is completely different from the typical memory as described above. A conventional thin film transistor 400 is shown in FIG. 4 as having a source region 402 and a drain region 404 formed in a polycrystalline silicon semiconductor layer 406. A gate oxide (SiO.sub.2) layer 408 overlies substrate 406 with its source region 402 and drain region 404. A gate 410 is formed on gate oxide 408. In conventional TFTs, gate oxide layer 408 is typically between 90 to 100 Angstroms thick.
In the normal operation of a TFT, electrons travel from source region 402 to drain region 404. In contrast to the memory devices described above, in normal operation electrons do not tunnel through SiO.sub.2 layer 408 and accordingly SiO.sub.2 layer 408 is not considered to experience tunneling damage during normal operation. Thus, whereas normal operation of a memory device can be destructive to SiO.sub.2 layer 304, SiO.sub.2 layer 408 of a TFT is not prone to destruction during normal operation.